Dice (chips of integrated circuits) form the most important foundation of modern information society. To drain operation power, dice include supply pads, such as power pads and ground pads respectively conducting power voltages and ground voltages to power routings and ground routings (both generally referred to as supply routings) inside the dice. To exchange signals with external circuitry, dice further include Input/output (I/O) pads conducting I/O signals to signal routings inside the dice, such that internal circuitry of the dice can exchange signals via the signal routings. A die can also be divided to different power domains; internal circuitry of different power domain operates in different supply voltage and/or ground voltage. However, ESD of high voltage also conducts to interior of a die via its pads and routings; to protect a die against ESD damage, a die is equipped with ESD protection circuits.
When an ESD event zaps between a signal routing and a supply routing, the ESD protection conducts ESD current between the two routings, so the ESD current does not accumulate to cause high voltage which damages internal circuitry coupled to the signal routing. Please refer to FIG. 1A illustrating a prior art ESD protection circuit 10, which is applied to an input pad PAD for protecting an internal circuit 12; for example, the internal circuit 12 includes a p-channel MOS transistors MP0 and an n-channel MOS transistor MN0, and gates of them are commonly coupled to a node ni for receiving signal via signal routing of a node ns. The internal circuit 12 is respectively coupled to direct-current (DC) voltages VCC (a power voltage) and GND (a ground voltage) via supply routings of nodes nv1 and nv2. In the internal circuit 12, gate-oxide tolerable voltage of the transistors MP0 and MN0 is denoted by a voltage Vt_ox; for dice of modern advanced manufacturing process, internal circuitry is formed by transistors of thin gate-oxide, thus the tolerable voltage Vt_ox is quite low. That is, when a voltage at the node ni is greater than the voltage Vt_ox, gate-oxide of the transistor(s) MP0 and/or MN0 will be damaged.
To protect gate-oxide of the transistors MN0 and MP0, the prior art ESD protection circuit 10 includes a primary ESD protection element N1, a primary ESD protection element P1 and a secondary protection circuit formed by a resistor R0 and two transistors N0 and P0. The primary ESD protection element N1 is coupled between the nodes ns and nv2, and the primary ESD protection element P1 is coupled between the nodes nv1 and ns. The transistors N0 and P0 are respectively n-channel and p-channel MOS transistors; a gate and a source of the transistor N0 are commonly coupled to the node nv2, and a drain of the transistor N0 is coupled to the node ni; a gate and a source of the transistor P0 are commonly coupled to the node nv1, and a drain of the transistor P0 is coupled to the node ni.
Operation of the ESD protection circuit 10 is described as follows. When ESD does not occur, the primary ESD protection elements N1 and P1, as well as the transistors N0 and P0, do not conduct. When ESD occurs between the nodes ns and nv2, a rapidly rising voltage V_ESD will be built at the node ns if the primary ESD protection element N1 does not conduct first or excessive ESD current flows through the primary ESD protection element N1 despite that the primary ESD protection element N1 has conducted first; consequently, the node ni is conducted to the node nv2 by breakdown conduction of the transistor N0 if the voltage V_ESD is positive (with respect to the node nv2) or by conduction of a forward-biased parasitic diode of the transistor N0 if the voltage V_ESD is negative. Therefore, a voltage Vg at the node ni can be calculated by: Vg=Vbd_mos+(V_ESD−Vbd_mos)*Rmos/(R0+Rmos); where the voltage Vbd_mos is a voltage across the node ni and nv2 when the transistor N0 conducts, the resistor Rmos is an equivalent resistance between the nodes ni and nv2 when the transistor N0 conducts by breakdown.
To protect the gates of the transistors MP0 and MN0, the ESD protection circuit 10 needs to keep the voltage Vg of the node ni lower than the gate-oxide tolerable voltage Vt_ox. In other words, designers of the prior art ESD protection circuit 10 should design dimensions of the transistor N0 according to circuit model of transistor breakdown, and thus derive resistance of the resistor R0. However, while simulating behavior of MOS transistor by circuit simulation software (e.g., SPICE), circuit model for simulating channel conduction (the conduction via carrier channel between drain and source formed by inversion layer under gate-oxide) is more accurate, and circuit model for simulating breakdown conduction is less accurate; therefore, it is difficult to correctly consider operation of breakdown conduction, design and implementation of the prior art ESD protection circuit 10 are consequently impacted.
Furthermore, other design and application issues exist for the prior art ESD protection circuit 10. If the transistors MN0/MP0 are transistors of thin gate-oxide, the transistors N0/P0 should be implemented also by transistors of thin gate-oxide to obtain better protection, but leakage current will therefore be larger, and equivalent capacitance also becomes higher to increase loading at the node ni and compromise high speed signal transmission. If the transistors N0/P0 are of thick gate-oxide, breakdown voltage for transistor breakdown conduction is greater, the transistors are thus more difficult to turn on timely and rapidly, and operation of ESD protection is hence degraded.
On the other hand, an ESD protection circuit formed by series diodes, as shown in FIG. 1B, is mentioned in “CDM Effect on a 65 nm SOC LNA”, p. 381, EOS/ESD Symp., 2010 by Worley et al. and U.S. Pat. No. 5,530,612; it protects gate of a transistor MN1 by diodes Da, Db1 and Db2. Nevertheless, this prior art ESD protection circuit also suffers pitfalls. A diode forms cathode and anode respectively by an n-well and a p-doped region in the n-well; as multiple diodes (e.g., the diodes Db1 and Db2) have to be serially coupled, there will be multiple n-wells. Since every two n-wells must be separated by a considerable distance and each n-well must be enclosed by a guard ring, the prior art ESD protection circuit suffers from larger layout area and lower area usage efficiency. In addition, p-doped region, n-well and p-substrate of ground voltage form a pnp leakage path of Darlington pair toward ground, thus more leakage current is conducted. Furthermore, in the prior art ESD protection circuit, while anodes and cathodes of the series diodes are coupled between a first node and a second node, an additional diode of opposite direction (e.g., the diode Da) must also be included; the diode of opposite direction has its anode and cathode respectively coupled to the second node and the first node for conducting ESD current from the second node to the first node. This diode of opposite direction occupies additional layout area.